The growing complexity of modern devices, especially in CMOS circuits, is the reason for the increased usage of simultaneously switching logic and I/O circuits on the chips which in turn have contributed to an increase in mid and high frequency power noise. In order to increase or save system performance, many efforts have been made in the past to protect sensitive circuits, such as PLLS, from being exposed to any power noise.
Phase locked loops, herein after PLLs, are sensitive to all noise, especially to mid and high frequency power noise. Such noise exposure can result in an output jitter which impacts the cycle time and the overall system performance. In the past, efforts to reduce the power noise, had included the placement of many different capacitors (of mixed types) on modules and on boards.
Voltage controlled oscillators, hereinafter VCOs, are the most power noise sensitive circuit in the PLL circuit. The state of the art VCO power filter designs use either off-chip filter capacitors or on-chip (integrated) capacitors for stabilizing voltage.
Due to design efforts, assembly costs and area consumption on modules and boards using the off-chip filter implementation is very expensive. This solution is also less effective due to the high parasitics elements of the and the path (R,L) intrinsic on the device. Furthermore, the off-chip filter implementation is limits its application since the parasitic elements prevent the high speed current transfer from the off-chip capacitor to the chip level.
On-chip VCOs are usually implemented using a multivibrator circuit where the oscillation is controlled by charging and discharging of an on-chip capacitor. A common application for such a circuit is in an optical high speed data link, which usually houses a serializer VCO and a deserializer VCO on the same module. These VCOs are especially sensitive to power supply noises, other VCOs and data patterns which have the same frequency component as the VCO operating frequency, but are asynchronous with each other. The type of noise in such circuits is usually referred to as near frequency noise. Sufficient amount of near frequency noise can override the control voltage input to the VCO and cause the PLL, (which houses the VCO ), to lose the phase lock. Any noise which contains odd harmonic frequencies (of the fundamental wave) will also affect the VCO although the sensitivity is not as dominant as the fundamental wave frequency itself.
The on-chip implementation is also limited due to low on-chip capacitance values.
IBM TDB, Vol. 34, No. 11, April 1992, p. 351-352 discloses an interface circuit that converts a differential input voltage to two equal bias currents which can be used to drive a VCO. The circuit is inherently high in noise rejection due to the differential circuitry used. Noise rejection is also improved by introducing noise roll-off capacitors in the interface biasing. The low capacitance requires only on-chip (integrated) capacitors.
In U.S. Pat. No. 5,191,301 there is disclosed a highly stable, high frequency VCO for phase locked loops, which VCO is adapted to be fully integrated on a single silicon chip and is operable over a wide frequency range without using off-chip capacitors.
U.S. Pat. No. 5,504,459 describes a filter network for a PLL circuit having a VCO with a control input and a bias input. The filter network includes a first filter circuit and a second filter circuit. The first filter circuit provides both a "pole" and a "zero" to the transfer function of the PLL. The second filter circuit is coupled between the control input and the bias input to the VCO.
An on-chip voltage controlled oscillator for use in an analog phase locked loop is described in U.S. Pat. No. 5,604,466. The VCO receives power from a voltage regulator which greatly reduces the noise seen by the VCO. The voltage regulator includes a passive filter coupled to the regulated power supply for attenuating high frequency noise from the regulated power supply, and for supplying power from the power supply to the voltage regulator, whereby the passive filter comprises a first resistor-capacitor pair for attenuating noise frequencies higher than a first threshold, and a second resistor-capacitor pair for attenuating noise frequencies higher than a second threshold.
However, the above-mentioned solutions have certain disadvantages. For example, due to parasitics, the above-mentioned solutions all have a limited electrical efficiency. The fact that, according to the above mentioned proposals, it is desirable to integrate all of the components of the VCO into a single silicon chip results in large area consumption on the module and/or board. Furthermore, placing a mix of different capacitor types in high quantities on the module and/or board leads to high component costs resulting from the need for complex assembly process leading to high assembly costs.